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检索到 2 条 责任者=Xia, Yuwen 的结果    

 


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  1. 西文非书资料1.Verilog digital system design Register transfer level synthesis, testbench, and verification = Ve... Y/TP312/N316-2

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    Navabi, Zainalabedin.
    Publishing House of Electronics Industry : 2007.
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  2. 西文图书2.Verilog digital system design : Register transfer level synthesis, testbench, and verification =... TP312/N316-2

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    Zainalabedin Navabi著 ; 夏宇闻改编.
    Publishing House of Electronics Industry ; 2007.
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