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• 099 __ |a CAL 022008034269

• 100 1_ |a Navabi, Zainalabedin.

• 245 10 |a Verilog digital system design : |b Register transfer level synthesis, testbench, and verification = Verilog数字系统设计 ： RTL综合、测试平台与验证 / |c Zainalabedin Navabi著 ; 夏宇闻改编.

• 246 31 |a Verilog数字系统设计 : |b RTL综合、测试平台与验证

• 250 __ |a 2nd ed.

• 260 __ |a Beijing : |b Publishing House of Electronics Industry ; |b 美国麦格劳－希尔教育出版社, |c 2007.

• 300 __ |a 17, 316 p. : |b ill. ; |c 24 cm. + |e 1 CD-ROM (4 3/4 in.)

• 440 _0 |a 国外电子与通信教材系列.

• 500 __ |a Adaptation of: Verilog digital system design, Register transfer level synthesis, testbench, and verification / Navabi, Zainalabedin. 384 p.

• 504 __ |a Includes bibliographical references.

• 534 __ |p Reprint. Originally published: |c McGraw-Hill Companies, c2006. |b 2nd ed. |z 0071445641

• 650 _0 |a Verilog (Computer hardware description language)

• 650 _0 |a Electronic digital computers |x Computer-aided design.

• 700 12 |a Navabi, Zainalabedin. |t Verilog digital system design. |s 2nd ed.

• 700 1_ |a Xia, Yuwen |9 (夏宇闻)

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