机读格式显示(MARC)

• 000 01370cam a2200361 i 4500

• 001 0000642050

• 003 SCNU

• 005 20180919150700.0

• 008 180526s2018 cc a 000 0 eng d

• 020 __ |a 9787121334214

• 040 __ |a PUL |b eng |e rda |c PUL |d PUL

• 093 __ |a TP312 |2 5

• 099 __ |a CAL 022018044739

• 100 1_ |a Hwang, Enoch O., |e author.

• 245 10 |a Digital system design with Verilog and VHDL = 数字系统设计 (Verilog & VHDL版) / |c Enoch O. Hwang著 ; 阎波, 朱晓章, 姚毅改编.

• 246 31 |a 数字系统设计 (Verilog & VHDL版)

• 246 31 |a 数字系统设计 : |b Verilog and VHDL版

• 250 __ |a Second edition.

• 264 _1 |a Beijing : |b Publishing House of Electronics Industry, |c 2018.

• 300 __ |a 14, 405 pages : |b illustrations ; |c 26 cm.

• 336 __ |a text |b txt |2 rdacontent

• 337 __ |a unmediated |b n |2 rdamedia

• 338 __ |a volume |b nc |2 rdacarrier

• 490 0_ |a 国外电子与通信教材系列

• 500 __ |a Adaptation of : Digital logic and microprocessor design with interfacing, 2nd ed. ISBN : 9781305859456, published by Cengage Learning, 2016.

• 650 _0 |a Logic design |x Data processing.

• 650 _0 |a Microprocessors |x Design and construction.

• 650 _0 |a VHDL (Computer hardware description language)

• 700 1_ |a Yan, Bo |9 (阎波)

• 700 1_ |a Zhu, Xiaozhang |9 (朱晓章)

• 700 1_ |a Yao, Yi |9 (姚毅)

• 920 __ |a 242430 |z 1

• 950 __ |a SCNU |f TP312/H991-2