机读格式显示(MARC)

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• 001 0000408697

• 003 SCNU

• 005 20090910174426.0

• 008 090506r20092008cc a b 001 0 eng d

• 020 __ |a 9787115195982

• 040 __ |a PUL |c PUL

• 082 04 |a 621.3815/2 |2 21

• 093 __ |a TN432 |2 4

• 099 __ |a CAL 022009061828

• 100 1_ |a Sutherland, Ivan Edward, |d 1938-

• 245 10 |a Logical effort : |b designing fast CMOS circuits = 高速CMOS电路设计Logical Effort方法 / |c Ivan Sutherland, Bob Sproull, David Harris著.

• 246 31 |a 高速CMOS电路设计Logical Effort方法

• 260 __ |a 北京 : |b 人民邮电出版社, |c 2009.

• 300 __ |a 2, 239 p. : |b ill. ; |c 26 cm.

• 490 0_ |a 图灵原版电子与电气工程系列

• 504 __ |a Includes bibliographical references (p. [233]) and index.

• 534 __ |p Reprint. Originally published: |c San Francisco, Calif. : Morgan Kaufmann Publishers, c1999.

• 650 _0 |a Metal oxide semiconductors, Complementary |x Design and construction.

• 650 _0 |a Logic design.

• 650 _0 |a Delay faults (Semiconductors)

• 700 1_ |a Bob, Robert F.

• 700 1_ |a Harris, David |q (David F.)

• 950 __ |a SCNU |f TN432/S966

• 999 __ |t C |A zxq |a 20090910 17:41:47 |M zxq |m 20090910 17:44:26 |G zxq |g 20090910 17:44:48

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• 991 __ |a 022009000723

• 907 __ |a SCNU |f TN432/S966