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题名/责任者:

Verilog digital system design : Register transfer level synthesis, testbench, and verification = Verilog数字系统设计 ： RTL综合、测试平台与验证 / Zainalabedin Navabi著 ; 夏宇闻改编.

版本说明:

2nd ed.

出版发行项:

Beijing : Publishing House of Electronics Industry ; 美国麦格劳－希尔教育出版社, 2007.

ISBN:

9787121052415

ISBN:

9787894854612 (CD-ROM)

载体形态项:

17, 316 p. : ill. ; 24 cm. + 1 CD-ROM (4 3/4 in.)

变异题名:

Verilog数字系统设计 : RTL综合、测试平台与验证

丛编题名:

国外电子与通信教材系列.

个人责任者:

Navabi, Zainalabedin.

附加个人名称:

Navabi, Zainalabedin. Verilog digital system design. 2nd ed.

附加个人名称:

Xia, Yuwen

论题主题:

Verilog (Computer hardware description language)

论题主题:

Electronic digital computers-Computer-aided design.

中图法分类号:

TP312

一般附注:

Adaptation of: Verilog digital system design, Register transfer level synthesis, testbench, and verification / Navabi, Zainalabedin. 384 p.

书目附注:

Includes bibliographical references.

原版附注:

Reprint. Originally published: McGraw-Hill Companies, c2006. 2nd ed. 0071445641

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